[IBMMot94] IBM Microelectronics and Motorola Inc., “The PowerPC Microprocessor Family: The Programming Environments,” IBM Microelectronics Document MPRPPCFPE-01, Motorola Document MPCFPE/AD (9/94). [IBM99] IBM Microelectronics, “IBM chip advances spur “sy

The DIVA (Data IntensiVe Architecture) system incorporates Processing-In-Memory (PIM) chips as smart-memory coprocessors to a microprocessor, with a separate memory-to-memory interconnect, thus exploiting the inherent memory bandwidth both on chip and across the system. DIVA targets several classes of bandwidth-limited applications, including multimedia applications and pointer-based and sparse-matrix computations. The DIVA project is building a prototype workstation-class system using VLSI PIM chips in place of standard DRAMs to demonstrate these concepts. We have recently fabricated the prototype PIM VLSI device. In this paper, we describe for the first time the DIVA PIM chip architecture, and in particular, its memory unit and its wide datapaths for exploiting bandwidth in computation, memory access and communication. We present detailed simulation results on eight benchmark applications. When just a single PIM chip is used, we still achieve a speedup of 3.3X over host-only execution. We show the contributions leading to this speedup from lower memory stall times, and benefits from 256-bit WideWord datapaths. Much more significant improvements are possible by exploiting coarsegrain parallelism across 32-64 PIM chips, the planned scale of the DIVA system, but these 1-PIM results suggest that A PIM-based architecture can yield significantly higher performance than a multiprocessor of a similar scale, and at a much reduced hardware cost.